(a) Field of the Invention
The invention relates to a detection system and method and, more particularly, to a detection system and method capable of detecting the processing speed of an integral circuit (IC).
(b) Description of the Related Art
Typically, each IC product may tend to have a different processing speed due to different factors, e.g. the situation of the environment, the stability of temperature, etc, during the manufacturing processes. However, since all IC products in the same batch must have the same processing speed that conform to a specific specification, they must be ranked according to their respective processing speeds, and then speed compensation is made thereon to allow all IC products in the same batch to have identical processing speeds.
FIG. 1 shows a conventional detection system for detecting the processing speed of an IC. The detection system 10 includes a ring oscillator 11 built inside the IC, and an external test unit 12 built outside the IC. The external test unit 12 includes a frequency elimination device 121 and a test platform 122. Alternatively, the frequency elimination device 121 of the external test unit 12 may be built inside the IC. In a typical detection of the processing speed of the IC, the ring oscillator 11 outputs an oscillation frequency signal Hf, which is in positive correlation to the processing speed, to the external test unit 12 to allow the test unit 12 to detect the processing speed of the IC. Then, all ICs in the same batch are ranked according to their respective processing speeds, and, subsequently, the speed compensation is made thereon.
However, though the ring oscillator 11 and the external test unit 12 together may accurately detect the processing speed of an IC, the frequency of the oscillation frequency signal Hf, about 1 GHz to 2 GHz, is considerably high. Since a typical test platform may increase its detecting frequency range up to only several hundreds of MHz, the frequency elimination device 121 that consists of multiple frequency eliminators 1211 is additionally required to lower the frequency of the oscillation frequency signal Hf to an accepted detection range for the test platform 122.
Further, since the test platform becomes more expensive as a broader detecting frequency range is provided, the cost of the test platform is reduced when the frequency of the oscillation frequency signal Hf is lowered. Thus, the number of the frequency eliminators 1211 must be increased to the extent that up to more than three, such as five or ten frequency eliminators 1211. However, it is clearly seen that the overall cost and power consumption of the test unit 12 are elevated as the number of the frequency eliminators 1211 is increased. Besides, in case the numerous frequency eliminators 1211 are built inside an IC, the occupied space of an IC will inevitably expand.
On the other hand, the ring oscillator 11 and the external test unit 12 that operate at a high frequency may also result in high power consumption.